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Resistive RAM, nanowire tunneling FETs, Surface plasmon polariton waveguides- Shifting Scenario in Computational Nanoelectronics

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Seminar Details
Presenter Name: 
Prof. Zhiping Yu
Date: 
Wednesday, September 1, 2010 - 2:00pm
Location: 
changed to MCLD 418
Seminar Abstract: 

To sustain the steady improvement in speed, scale, and saving of power for silicon-based ICs while the end of ITRS roadmap looms, new materials, structures, and devices (MSD) are urgently needed.
This talk covers three alternative structures to complement planar CMOS technology from numerical simulation point of view:
1. Resistive RAM (RRAM) made of carbon and TiO for non-volatile memories
2. Nanowire tunneling FETs (NW-tFETs) with SiGe heterojunction for low-power, high-performance logic devices
3. Surface plasmon polariton (SPP) waveguide for propagation of THz signals on chip
Different levels of physics complexity are incorporated in the simulation: from macroscopic drift-diffusion carrier transport including tunneling and EM solver to molecular dynamics (MD) and quantum transport at atomistic level. The simulation of SPP also involves interplay with optics.
To address the need for study of novel nanoelectronic devices such as graphene narrow-ribbon (GNR) transistors, an EHT (extended Hücker theory) plus NEGF (non-equilibrium Green’s function) code has been developed to efficiently calculate the bandstructure and evaluate I-V characteristics.
Overall, these nanotechnology CAD activities in Tsinghua will be described.

Presenter Biography: 

Prof. Zhiping Yu graduated from Tsinghua University, Beijing, China, in 1967 with B.S. degree, he received M.S. and Ph. D degrees from Stanford University, Stanford, CA, US in 1980, and 1985, respectively.

He is presently the professor of Institute of Microelectronics, Tsinghua University, Beijing, China and a visiting professor in EE Dept. at Stanford University, CA, USA. From 1989 to 2002, he has been a senior research scientist in EE Dept. at Stanford, while serving the faculty member in Tsinghua. Between 2003 and 2005, he held Pericom (San Jose, USA) Microelectronics Professorship and since 2006 he holds Novellus (San Jose, USA) Microelectronics Professorship, both in Tsinghua.

His research interests include device simulation for nanoscale MOSFETs, quantum transport in nanoelectronic devices, compact circuit modeling of passive and active components in RF CMOS, and numerical analysis techniques.

Dr. Yu has published more than 300 technical papers and is the co-author of a book on TCAD (Technology CAD) in English. A co-authored book on RF CMOS circuit design (in Chinese) was published by Tsinghua University Press in 2006.

Dr. Yu is an IEEE Fellow and served as the Associate Editor of IEEE Trans. CAD of IC & Systems (ICCAD) from 1996 to 2005. He now serves as member of IEEE EDS Nanotechnology Committee since 2006.