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A variable rate constraint length K=5 Viterbi decoder for 12 Mb/s

Publication Type:

Conference Paper


1993 Canadian Conference on Electrical and Computer Engineering (Cat. No.93TH0590-0), IEEE, Volume vol.1, Vancouver, BC, Canada, p.582-5 (1993)



application specific integrated circuits; CMOS integrated circuits; codecs; convolutional codes; decoding; digital signal processing chips; maximum likelihood estimation; memory architecture; parallel architectures; VLSI


Describes a fully testable variable rate Viterbi decoder chip capable of decoding convolutional codes ranging from rate 7/8 to 1/4 derived from the same 1/2 rate code. The architecture of the Viterbi decoder is bit-serial node-parallel to save interconnect area but still achieve high speed decoding. Modulo normalization of the surviving path metrics, arranging the memory elements of the path memory as sets of butterflies, and custom layout are the key for reducing the Si area. Newly developed area efficient testing schemes achieve 99.9\% single stuck-at-fault coverage, while requiring <5\% hardware overhead