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Time domain multiplexed TAM: implementation and comparison

Publication Type:

Conference Paper


Proceedings Design, Automation and Test in Europe Conference and Exhibition, IEEE Comput. Soc, Munich, Germany, p.732-7 (2003)



automatic test equipment; automatic testing; built-in self test; integrated circuit testing; optimisation; system-on-chip; time division multiplexing


One of the difficult problems which core-based system-on-chip (SoC) designs face is test access. For testing the cores in a SoC, a special mechanism is required, since they are not directly accessible via chip inputs and outputs. In this paper we introduce a novel Test Access Mechanism (TAM) based on time domain multiplexing (TDM-TAM). This TAM is P1500 compatible and uses a P1500 wrapper The TAM characteristics are its flexibility, scalability, and reconfigurability. The proposed TAM is compared with two other approaches: a serial threading approach analogous to the IEEE] 149.1 standard (Serial TAM) and a packet-switching test network (NIMA). A network-processing engine SoC is used as a platform to compare the different TAMs. Results show that in most cases, TDM is the most effective TAM in both test time and overhead area