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System-on-chip: reuse and integration

Publication Type:

Journal Article

Source:

Proc. IEEE (USA), Volume 94, p.1050-69 (2006)

URL:

http://dx.doi.org/10.1109/JPROC.2006.873611

Keywords:

design for testability; formal verification; high level synthesis; industrial property; integrated circuit design; integrated circuit testing; system-on-chip

Abstract:

Over the past ten years, as integrated circuits became increasingly more complex and expensive, the industry began to embrace new design and reuse methodologies that are collectively referred to as system-on-chip (SoC) design. In this paper, we focus on the reuse and integration issues encountered in this paradigm shift. The reusable components, called intellectual property (IP) blocks or cores, are typically synthesizable register-transfer level (RTL) designs (often called soft cores) or layout level designs (often called hard cores). The concept of reuse can be carried out at the block, platform, or chip levels, and involves making the IP sufficiently general, configurable, or programmable, for use in a wide range of applications. The IP integration issues include connecting the computational units to the communication medium, which is moving from ad hoc bus-based approaches toward structured network-on-chip (NoC) architectures. Design-for-test methodologies are also described, along with verification issues that must be addressed when integrating reusable components