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Study of Near-surface Stresses in Silicon around Through Silicon Vias at Elevated Temperatures by Raman spectroscopy and Simulations

Publication Type:

Journal Article


IEEE Transactions on Device and Material Reliability, Volume 15, p.142-148 (2015)



Near-surface stress distribution around Cu through silicon vias (TSVs) was studied by micro-Raman spectroscopy along with finite element analysis (FEA) from room temperature to 100 ⁰C. Temperature dependent measurements along with simulations revealed that the stresses near TSVs can have two components: 1) pre-existing stress before copper filling, and 2) coefficients of thermal expansion (CTE) mismatch-induced stress. The CTE-mismatch-induced stress resulted mobility change and keep-out zone (KOZ) at elevated temperatures were also estimated, where the KOZ was defined as the region with a mobility change larger or equal to 10%. Higher temperatures were shown to reduce the CTE-mismatch-induced stress component, and resulted in the shrinkage of KOZs in Si. The pre-existing stress was shown to be significant in a region equal or larger than the KOZs induced by CTE-mismatch-induced stress only and should be characterized and considered in the KOZ determination and circuit design.

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