Simulation of a Low-Voltage Organic Transistor Compatible With Printing Methods
Publication Type:Journal Article
Source:Electron Devices, IEEE Transactions on, Volume 55, Number 1, p.276 -282 (2008)
Keywords:OFET;OFET simulation;OMESFET design;OMESFET mobility;amorphous semiconductor layers;depletion mode;localized states;low-cost electronics;low-voltage organic transistor;on-off current ratios;organic Schottky junction;organic field-effect transistors;organi
The use of printing methods to deposit organic semiconductors promises to enable low-cost electronics. However, printing processes deposit thick and amorphous semiconductor layers that result in poorly performing organic field-effect transistors (OFETs) that generally are not appropriate for incorporation into commercially viable circuits. Another undesirable property of OFETs is their high operating voltage (~40 V). Organic metal-semiconductor FETs (OMESFETs) are proposed as alternatives to OFETs for use with printing methods. OMESFETs operate at low voltages (~5 V) and are expected to show better on/off current ratios than OFETs in a thick-film semiconductor. Simulations of OFETs and OMESFETs are performed assuming regioregular poly (3-hexylthiophene) (rr-P3HT) as the amorphous semiconductor layer with localized states close to the band edge. The results of the simulations show a current ratio of 104 in the OMESFET and of 700 in the OFET for a 400-nm-thick semiconductor layer. Because the OMESFET operates in the depletion mode, versus the accumulation mode in the OFET, the calculated mobility in the OMESFET is two orders of magnitude smaller than that in the OFET. Simulations suggest that the OMESFET design offers performance advantages over printable OFETs, where low-voltage operation is demanded.