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A retention-aware test power model for embedded SRAM

Publication Type:

Conference Paper


Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference 2005 (IEEE Cat. No.05EX950C), IEEE, Volume Vol. 2, Shanghai, China, p.1180-3 (2005)


embedded systems; integrated circuit modelling; integrated circuit testing; logic testing; optimisation; scheduling; SRAM chips; system-on-chip


This paper addresses the test power model problem for embedded SRAMs (e-SRAMs). Previous researches treat e-SRAMs the same as other SoC core and use a "single-rectangle" power model to describe their test power consumption. This leads to significant waste of test time since e-SRAM test usually includes a long period of "zero" power consumption for the detection of data retention faults, This paper takes advantage of this "zero" power period and proposes a "retention-aware" test power model for e-SRAMs. The proposed model is evaluated and its impact on test time reduction is reported for various scenarios in terms of retention test duration, memory capacities, test algorithm complexities, etc. A formula is derived to predict the maximum test time reduction when the "zero" power period is fully utilized in a SoC environment