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Reducing embedded SRAM test time under redundancy constraints

Publication Type:

Conference Paper


Proceedings. 22nd IEEE VLSI Test Symposium, IEEE Comput. Soc, Napa Valley, CA, USA, p.237-42 (2004)



integrated circuit testing; redundancy; SRAM chips; system-on-chip


Increasingly dense SRAMs of various bit capacities, embedded within current and future systems-on-a-chip (SoC) designs, command not only additional complexity due to required redundancy schemes, but also present serious challenges in regards to testing. In particular, the time needed for testing data retention faults (DRFs) and non-DRFs is growing rapidly. In this paper, we consider the overall production gain (OPG) and delay time associated with the testing of DRFs as the two selection factors for classifying embedded SRAMs, where OPG quantifies the trade-offs between yield and redundancy area overhead. These embedded SRAMs are categorized into four categories for testing non-DRFs and DRFs. Since both factors above are related to memory capacity, the four categories are named as very small, small, large, and very large types. According to this simple classification, we generate a set of four March test algorithms from an existing March SRD algorithm for each category respectively. As a comparison with March SRD, our investigations reveal that test time can generally be at least halved down to 22 nm technology for all capacity e-SRAMs with different IO numbers without losing defect coverage. The evaluation results also show that this reduction ratio is always no less than 50\% for those with larger and larger and larger capacity predicted for future e-SRAMs in ITRS documents no matter what complex the comparison algorithms besides March SRD are