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Performance of signature analysis: a survey of bounds, exact, and heuristic algorithms

Publication Type:

Journal Article

Source:

Integr. VLSI J. (Netherlands), Volume 13, p.17-38 (1992)

URL:

http://dx.doi.org/10.1016/0167-9260(92)90016-R

Keywords:

built-in self test; data compression; error statistics; integrated circuit testing; logic testing; VLSI

Abstract:

Built-in self-test (BIST) is emerging as one of the most promising solutions for testing large and complex integrated circuits. In BIST, high test quality is generally achieved by applying a large number of test patterns to the circuit under test. The large amount of ensuing test response data makes test response compaction mandatory in most cases. Response, compaction implies an information loss that translates into the possibility that a faulty circuit be declared good. Such an erroneous diagnosis is known as being caused by an aliasing error. For any BIST compaction scheme, it is crucial to have a measure of the possible aliasing. The scheme for performing compaction that has thus far received the most attention is known as signature analysis, which is implemented using linear feedback shift registers. Several papers on the probability of aliasing associated with signature analysis, under various error models, have recently been published. Alternative approaches have been proposed for computing such probabilities, ranging from computationally intensive exact solutions, to bounds, and approximate heuristic solutions. The authors present a survey of these recent contributions and emphasize their important similarities and differences