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A packet switching communication-based test access mechanism for system chips

Publication Type:

Conference Paper


Proceedings IEEE European Test Workshop. ETW 2001, IEEE Comput. Soc, Stockholm, Sweden, p.81-6 (2001)


application specific integrated circuits; automatic test pattern generation; built-in self test; embedded systems; integrated circuit testing; microprocessor chips; packet switching


In this paper, a Test Access Mechanism (TAM) architecture based on a packet switching communication network is presented. The basic goal is to develop a modular, generic, and configurable TAM. The proposed architecture provides a modular TAM that provides two levels of scalability, i.e., design-version scalability and multi-level scalability. Core access time and interconnect length models and simulation results for the proposed architecture are presented and compared to that of a bus-based TAM