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Open defects detection within 6T SRAM cells using a No Write Recovery Test Mode

Publication Type:

Conference Paper

Source:

Proceedings. 17th International Conference on VLSI Design, IEEE Comput. Soc, Mumbai, India, p.493-8 (2004)

URL:

http://dx.doi.org/10.1109/ICVD.2004.1260969

Keywords:

design for testability; fault simulation; integrated circuit testing; SRAM chips

Abstract:

The detection of all open defects within 6T SRAM cells is always a challenge due to the significant test time requirements. This paper proposes a new design-for-test (DFT) technique that we refer to as No Write Recovery Test Mode (NWRTM) to detect all open defects, some of which produce Data Retention Faults (DRFs) but are undetectable by typical March tests. We demonstrate the effectiveness of our proposed technique by only applying it to fault-free memory cells and faulty cells with those undetectable defects but all the open defects are covered since our DFT technique is implemented by simply adding extra test cycles into typical March tests. Two 6T SRAM cell models, one a high-speed version and the other a low-power one, representing extreme cases according to traditional design methodologies, were designed to validate our proposed NWRTM at the circuit level. Simulation results show that our NWRTM amounts to a shorter total test time and improved open defect detection capability. In addition, in comparison to other DFT techniques, NWRTM requires the least additional design effort, and imply less area and no performance penalties