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Non-intrusive testing of high-speed CML circuits

Publication Type:

Conference Paper

Source:

Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259), IEEE Comput. Soc, Singapore, p.172-8 (1998)

URL:

http://dx.doi.org/10.1109/ATS.1998.741610

Keywords:

bipolar logic circuits; current-mode logic; fault location; high-speed integrated circuits; integrated circuit testing; logic testing; production testing

Abstract:

A new methodology for production phase testing of catastrophic short and open faults in Current Mode Logic (CML) circuits is proposed. The catastrophic faults induced in differential input CML circuits due to manufacturing defects are detected by manipulating the voltage levels of the inputs. The non-intrusive tests include functional (at-speed) tests, Idd test, and a new test called common-mode test (CMT). Two high-speed interface circuits, a 622 Mbps SONET SIPO (Serial-in-Parallel-Out) and a PISO (Parallel-In-Serial-Out) are used as examples to illustrate the effectiveness of the tests. Using all three tests, SPICE simulations show that 88-90\% fault coverage of catastrophic faults can be detected