User login

A multiple signature compaction scheme for BIST

Publication Type:

Journal Article

Authors:

Wu, Y.; Ivanov, A.

Source:

Microelectron. J. (UK), Volume 23, p.205-14 (1992)

URL:

http://dx.doi.org/10.1016/0026-2692(92)90012-P

Keywords:

automatic testing; built-in self test; data compression; integrated circuit testing; logic testing

Abstract:

The approach of checking multiple signatures has recently received attention because of the associated advantages of small aliasing, easy computation of fault coverage, shorter average test time, and increased fault diagnosability. In this paper the authors propose a BIST multiple-signature compaction scheme that achieves negligibly small aliasing against reasonable extra hardware expenses compared with known standard single signature schemes and against less expenses than those incurred by other `low aliasing probability' schemes. Experimental results illustrate possible tradeoffs between the number of signatures, their width (number of bits) and hardware requirements