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A minimal hardware overhead BIST data compaction scheme

Publication Type:

Conference Paper

Authors:

Wu, Y.; Ivanov, A.

Source:

Proceedings of Fifth Annual IEEE International ASIC Conference and Exhibit (Cat. No.92TH0475-4), IEEE, Rochester, NY, USA, p.368-71 (1992)

URL:

http://dx.doi.org/10.1109/ASIC.1992.270217

Keywords:

binary sequences; built-in self test; data compression; integrated circuit testing; logic testing; shift registers

Abstract:

Existing data compaction schemes for built-in self-test (BIST) usually impose substantial hardware overhead. A minimal hardware overhead data compaction scheme is proposed that can achieve reasonably small aliasing with a hardware requirement as low as a one-stage linear feedback shift register (LFSR). Multiple signatures are checked, and all reference-signatures are made identical resulting in simple circuitry for checking the signatures. The proposed scheme is based on a simple manipulation of the fault-free output sequences from the circuit under test