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Minimal hardware multiple signature analysis for BIST

Publication Type:

Conference Paper

Source:

Digest of Papers. Eleventh Annual 1993 IEEE VLSI Test Symposium (Cat. No.93TH0537-1), IEEE Comput. Soc. Press, Atlantic City, NJ, USA, p.17-20 (1993)

URL:

http://dx.doi.org/10.1109/VTEST.1993.313314

Keywords:

built-in self test; integrated logic circuits; logic testing

Abstract:

Proposes a new BIST multiple intermediate signature analysis scheme which checks n signatures against a single reference. Therefore, the circuitry for checking n signatures is essentially the same as that for checking one signature. The scheme is based on a manipulation of the CUT's fault-free output sequence. No circuit modification is required. The cost for implementing the scheme is a small nonrecurring CPU time expenditure in the design phase. In return, the scheme yields significant recurring silicon area savings, and reduced aliasing