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Methodologies and algorithms for testing switch-based NoC interconnects

Publication Type:

Conference Paper


20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, IEEE Comput. Soc, Monterey, CA, USA, p.238-46 (2005)


buffer circuits; integrated circuit interconnections; integrated circuit testing; logic circuits; logic testing; network-on-chip


In this paper, we present two novel methodologies for testing the interconnect fabrics of network-on-chip (NoC) based chips. Both use the concept of recursive testing, with different degrees of parallelism in each case. Our test methodologies cover the logic switching blocks and the FIFO buffers that are the basic components of NoC fabrics. The paper concludes with test time evaluations for different NoC topologies and sizes