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An investigation of <i>pnp</i> polysilicon emitter transistors

Publication Type:

Journal Article

Source:

Solid-State Electron. (UK), Volume 33, Number 7, p.813 - 18 (1990)

URL:

http://dx.doi.org/10.1016/0038-1101(90)90060-R

Keywords:

bipolar transistors;digital simulation;elemental semiconductors;semiconductor device models;semiconductor technology;silicon;tunnelling;

Abstract:

The DC characteristics are computed for pnp polysilicon emitter transistors (PETs) in which a thin insulating layer is incorporated in the emitter structure. Both devices with, and without, a post-polysilicon deposition annealing treatment are modeled. The effects of the annealing are taken to be a reduction in the insulator thickness and the creation of a p-type monosilicon emitter region. The simulations reveal that moderate current gains, around 300, are possible with these devices

Notes:

emitter tunnel oxide layer;emitter thin insulating layer;DC characteristics;semiconductors;pnp polysilicon emitter transistors;PETs;annealing;insulator thickness;p-type monosilicon emitter region;current gains;polycrystalline Si emitter;Si-SiOx-Si;