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On fault coverage in VLSI built-in self-test with multiple intermediate signature analysis

Publication Type:

Conference Paper


1993 Canadian Conference on Electrical and Computer Engineering (Cat. No.93TH0590-0), IEEE, Volume vol.1, Vancouver, BC, Canada, p.449-52 (1993)



built-in self test; integrated circuit testing; logic testing; VLSI


This paper studies the fault coverage performance with multiple intermediate signature analysis. Two fault coverage models are presented. Unlike the results reported in the literature, these models reveal that the fault coverage with multiple intermediate signature analysis depends on the times when the signatures are checked. Experimental results on benchmark circuits are reported