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A fast diagnosis scheme for distributed small embedded SRAMs

Publication Type:

Conference Paper

Source:

Proceedings. Design, Automation and Test in Europe, IEEE Comput. Soc, Volume Vol. 2, Munich, Germany, p.852-7 (2005)

Keywords:

distributed memory systems; embedded systems; fault diagnosis; integrated circuit testing; SRAM chips; system-on-chip

Abstract:

The paper proposes a diagnosis scheme aimed at reducing the diagnosis time of distributed small embedded SRAMs (e-SRAMs). This scheme improves on one proposed previously (Huang, D.C. et al., Proc. Int. Conf. VLSI Design, p.397-402, 2001; Huang and Jone, W.B., IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.21, no.4, p.449-65, 2002). The improvements are mainly twofold. On one hand, the diagnosis of time-consuming data retention faults (DRFs), which is neglected by the diagnosis architecture of Huang et al., is now considered and performed via a DFT technique referred to as the "no write recovery test mode" (NWRTM). On the other hand, a pair comprising a serial-to-parallel converter (SPC) and a parallel-to-serial converter (PSC) is utilized to replace the bidirectional serial interface, to avoid the problems of serial fault masking and defect rate dependent diagnosis. Results from our evaluations show that the proposed diagnosis scheme achieves an increased diagnosis coverage and reduces diagnosis time compared to those obtained by Huang et al., with negligible extra area cost