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Fast detection of data retention faults and other SRAM cell open defects

Publication Type:

Journal Article


IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. (USA), Volume 25, p.167-80 (2006)



design for testability; fault simulation; integrated circuit testing; low-power electronics; SRAM chips


Detection of open defects in static random access memory (SRAM) cells, including those causing data retention faults (DRFs), is known to be difficult and time consuming. This paper proposes a novel design-for-test (DFT) technique that allows SRAMs to be tested at full speed for these defects. As a result, it achieves not only significant test time reduction but also full coverage of open defects, including those undetectable to previous solutions. The proposed technique is referred to as predischarge write test mode (PDWTM). Implementation of the proposed technique requires little design effort and imposes negligible hardware and performance penalties. Furthermore, the proposed technique can be easily merged with any March algorithm, thus resulting in full DRF and other SRAM cell open defect coverage. The proposed technique has been validated by SPICE simulation using both low-power and high-speed SRAM cells