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Evaluation of MP-SoC interconnect architectures: a case study

Publication Type:

Conference Paper

Source:

4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IEEE Comput. Soc, Banff, Alta., Canada, p.253-6 (2004)

URL:

http://dx.doi.org/10.1109/IWSOC.2004.1319889

Keywords:

integrated circuit design; multiprocessor interconnection networks; parallel architectures; performance evaluation; system-on-chip

Abstract:

Multiprocessor (MP-SoC) platforms are emerging as the latest trend in SoC design. These MP-SoCs consist of a large number of IP blocks in the form of functionally heterogeneous embedded processors. In this design paradigm, IP blocks need to be integrated using a structured interconnect template, for example, according to high-performance parallel computing architectures. A formal evaluation process is required before adopting a specific parallel architecture to SoC domain. Here, we propose an evaluation methodology based on performance metrics that include latency, throughput and silicon area requirements. As a case study, we present the results of such an evaluation for two MP-SoC interconnect topologies, i.e., the mesh and the butterfly fat-tree (BFT). This evaluation methodology can be extended to any other SoC interconnect topology without loss of generality