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Computing the error escape probability in count-based compaction schemes

Publication Type:

Conference Paper

Source:

1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.90CH2924-9), IEEE Comput. Soc. Press, Santa Clara, CA, USA, p.368-71 (1990)

URL:

http://dx.doi.org/10.1109/ICCAD.1990.129927

Keywords:

circuit layout CAD; fault location

Abstract:

A unified probabilistic model of count-based compaction is presented that relates the probability of occurrence of the `counted' events to a circuit's fault detection probabilities. This model enables an identical treatment to be made of all the different count-based techniques proposed to date, e.g., ones, transitions, edges, and spectral coefficients. Based on this model, the authors propose a computation technique for determining the error escape associated with these specific, as well as more general, count-based compaction techniques, under various error models