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Analog IP design flow for SoC applications

Publication Type:

Conference Paper


Proceedings of the 2003 IEEE International Symposium on Circuits and Systems (Cat. No.03CH37430), IEEE, Volume vol.4, Bangkok, Thailand, p.676-9 (2003)



analogue processing circuits; circuit CAD; integrated circuit design; phase locked loops; system-on-chip; voltage-controlled oscillators


The analog/mixed-signal (AMS) portion of the IC design process continues to be a major bottleneck, slowing the progress towards fully integrated system-on-chip (SoC) designs. A clear definition of reusable analog IP and an analog IP authoring flow has not emerged as yet, although many efforts are underway in industry and academia to establish these notions. In this work, practical definitions of analog IP and an associated design process is proposed A methodology is developed for analog IP hardening. The VCO of a phase locked loop (PLL) is chosen to illustrate the process due to the increasing importance of PLLs in SoC designs