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Accelerated path delay fault simulation

Publication Type:

Conference Paper

Source:

Digest of Papers. 1992 IEEE VLSI Test Symposium. 10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip (Cat. No.92TH0437-4), IEEE, Atlantic City, NJ, USA, p.1-6 (1992)

URL:

http://dx.doi.org/10.1109/VTEST.1992.232715

Keywords:

digital simulation; fault location; logic CAD; logic gates

Abstract:

Due to fanout in a circuit, the speed efficiency of existing path delay fault simulation algorithms suffers from redundant evaluations of many circuit nodes in the backtrace process of every simulation pass. This paper introduces two new concepts-subpath event sensitizability (SES) and subpath event sensitizability robustness (SESR). Based on these new concepts, the authors propose a new procedure for path delay fault simulation whereby each node of the simulated circuit is evaluated only once per simulation pass in the backtrace process. Experiments with the ISCAS'85 benchmark circuits show that the procedure accelerates path delay fault simulation significantly. The proposed procedure can be implemented for parallel pattern path delay fault simulation. The concepts of SES and SESR can also improve both CPU time and memory efficiency of path delay fault simulation if only a subset of all the paths is considered