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A 0.35 ?m CMOS comparator circuit for high-speed ADC applications

Publication Type:

Conference Paper


IEEE International Symposium on Circuits and Systems (ISCAS) (IEEE Cat. No. 05CH37618), IEEE, Volume Vol. 6, Kobe, Japan, p.6134-7 (2005)


analogue-digital conversion; CMOS integrated circuits; comparators (circuits); logic gates; preamplifiers; sample and hold circuits


A high-speed differential clocked comparator circuit is presented. The comparator consists of a preamplifier and a latch stage followed by a dynamic latch that operates as an output sampler. The output sampler circuit consists of a full transmission gate (TG) and two inverters. The use of this sampling stage results in a reduction in the power consumption of this high-speed comparator. Simulations show that charge injection of the TG adds constructively to the sampled signal value, therefore amplifying the sampled signal with a modest gain of 1.15. Combined with the high gain of the inverters, the sampled signals are amplified toward the rail voltages. This comparator is designed and fabricated in a 0.35 ?m standard digital CMOS technology. Measurement results show a sampling frequency of 1 GHz with 16 mV resolution for a 1 V input signal range and 2 mW power consumption from a 3.3 V supply. The architecture can be scaled down to smaller feature sizes and lower supply voltages