User login

A 0.18 ?m CMOS pipelined encoder for a 5 GS/s 4-bit flash analogue-to-digital converter

Publication Type:

Journal Article

Source:

Can. J. Electr. Comput. Eng. (Canada), Volume 30, p.183-7 (2005)

URL:

http://dx.doi.org/10.1109/CJECE.2005.1541749

Keywords:

analogue-digital conversion; CMOS digital integrated circuits; current-mode logic; MMIC; pipeline processing

Abstract:

A high-speed CMOS encoder intended for a 5 gigasample/second (GS/s) 4-bit flash analogue-to-digital converter (ADC) is presented. To meet the speed and power targets of the ADC, low-swing signalling is used in all the internal sub-blocks of the ADC, including the encoder, which is implemented in current-mode logic (CML). To further enhance the encoder's speed, two-stage pipelining is used. Details of the architecture are described. The proposed two-stage pipelined encoder as well as an encoder with no pipelining are designed and simulated in a 0.18 ?m CMOS technology, and their performances are compared. Simulation results predict a 40\% speed improvement for the pipelined encoder. The encoder circuit consumes 4 mW from a 1.8 V supply while operating at 5 GHz