Si stress in Si induced by Cu through-silicon vias (TSVs)
3D integration of integrated circuits is one of the major approaches in research to increase packing density, communication bandwidth and to reduce wire length and energy consumption. Through silicon via is one of the key technology in achieving 3D integration. Cu is used to fill TSVs, which also introduce thermal mismatch stress in the surrounding Si. This project investigate stress dependence on TSV microstructure and annealing process.