Application of printing methods in producing organic transistors has promised low-cost electronics, but a printed transistor has a poor performance due to the thick semiconductor layer. Also, most of organic transistors operate at high voltages (> 40V). We are investigating two types of organic transistors, OMESFET and dual gate transistor, to overcome the voltage problem and enhance the performance in a thick film transistor.
The first objective of this project is to eliminate the voltage problem in organic transistors by modification of the structure and geometry of the transistors. Most organic transistors have a Thin-Film Transistor (TFT) structure and are known as Organic Field-Effect Transistors (OFETs). A voltage range of 40 V is very typical in OFETs due to the small gate capacitance resulted from thick insulating layer between the gate and the semiconductor. Increasing the gate capacitance by reducing the insulating layer thickness requires the application of advance fabrication methods like evaporation which increases the capital cost of products, whereas the main advantage of the organic semiconductors over other materials such as silicon or amorphous silicon is the possibility to print devices with very low cost. In this research a low voltage organic transistor is developed by direct contact between the gate metal to the semiconductor. The device has a structure similar to Metal-Semiconductor Field-Effect Transistors (MESFETs) where the depletion region generated from the Schottky contact between the gate and the semiconductor controls the conductance between the drain and source terminals. Both the simulation and primary experimental results of the OMESFET indicate the low voltage operation of the transistor (<5 V). In simulation a current ratio of 10000 is obtained between the on and off states of the OMESFET. As a challenge in real OMESFET we are working on reducing the gate leakage current to achieve that current ratio.
In the other approach the combination of an OMESFET and an OFET is suggested to make a dual gate organic transistor. The performance of OFETs drops rapidly with an increase in the thickness of the semiconductor layer (> 50 nm). Application of printing methods as a low-cost fabrication process produces a relatively thick semiconductor layer (~200 nm) which causes low performance in OFETs. In dual gate organic transistors the depletion region from the OMESFET gate contact is employed to reduce the effective thickness and thereby improve performance in the OFET. Simulations and primary experimental results show improvements in the threshold voltage, the current ratio, and the output resistance of a dual gate transistor, when compared to those in an OFET of the same thickness.