%0 Journal Article %J Solid-State Electron. (UK) %D 1990 %T An investigation of pnp polysilicon emitter transistors %A Laser, A P %A Chu, K M %A Pulfrey, D L %A Maritan, C M %A Tarr, N G %K bipolar transistors;digital simulation;elemental semiconductors;semiconductor device models;semiconductor technology;silicon;tunnelling; %P 813 - 18 %U http://dx.doi.org/10.1016/0038-1101(90)90060-R %V 33 %X The DC characteristics are computed for pnp polysilicon emitter transistors (PETs) in which a thin insulating layer is incorporated in the emitter structure. Both devices with, and without, a post-polysilicon deposition annealing treatment are modeled. The effects of the annealing are taken to be a reduction in the insulator thickness and the creation of a p-type monosilicon emitter region. The simulations reveal that moderate current gains, around 300, are possible with these devices %Z emitter tunnel oxide layer;emitter thin insulating layer;DC characteristics;semiconductors;pnp polysilicon emitter transistors;PETs;annealing;insulator thickness;p-type monosilicon emitter region;current gains;polycrystalline Si emitter;Si-SiOx-Si; %9 article