%0 Conference Paper %B 2007 International Symposium on Networks-on-Chip %D 2007 %T Towards open network-on-chip benchmarks %A Grecu, C %A Ivanov, A %A Pande, R %A Jantsch, A %A Salminen, E %A Ogras, U %A Marculescu, R %C Princeton, NJ, USA %I IEEE Computer Society %K benchmark testing,integrated circuit design,integrated circuit reliability,integrated circuit testing,network-on-chip %P 8 pp. %X Measuring and comparing performance, cost, and other features of advanced communication architectures for complex multi core/multiprocessor systems on chip is a significant challenge which has hardly been addressed so far. This document outlines the top-level view on a system of benchmarks for networks on chip (NoC), which intends to cover a wide spectrum of NoC design aspects, from application modeling to performance evaluation and post-manufacturing test and reliability. For performance benchmarking, requirements and features are described for application programs, synthetic micro-benchmarks, and abstract benchmark applications. Then, it proposes ways to measure and benchmark reliability, fault tolerance and testability of the on-chip communication fabric. This paper introduces the main concepts and ideas for benchmarking NoCs in a systematic and comparable way. It will be followed up by a report that will define a benchmark framework and the syntax of interfaces for benchmark programs that will allow the community to build-up a benchmark suite %9 inproceedings