%0 Journal Article %J IEEE Trans. Comput. (USA) %D 2005 %T Performance evaluation and design trade-offs for network-on-chip interconnect architectures %A Pande, Partha Pratim %A Grecu, C %A Jones, M %A Ivanov, A %A Saleh, R %K computer architecture,integrated circuit interconnections,multiprocessing systems,performance evaluation,system-on-chip %P 1025-40 %U http://dx.doi.org/10.1109/TC.2005.134 %V 54 %X Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Power and wire design constraints are forcing the adoption of new design methodologies for system-on-chip (SoC), namely, those that incorporate modularity and explicit parallelism. To enable these MP-SoC platforms, researchers have recently pursued scaleable communication-centric interconnect fabrics, such as networks-on-chip (NoC), which possess many features that are particularly attractive for these. These communication-centric interconnect fabrics are characterized by different trade-offs with regard to latency, throughput, energy dissipation, and silicon area requirements. In this paper, we develop a consistent and meaningful evaluation methodology to compare the performance and characteristics of a variety of NoC architectures. We also explore design trade-offs that characterize the NoC approach and obtain comparative results for a number of common NoC topologies. To the best of our knowledge, this is the first effort in characterizing different NoC architectures with respect to their performance and design trade-offs. To further illustrate our evaluation methodology, we map a typical multiprocessing platform to different NoC interconnect architectures and show how the system performance is affected by these design trade-offs %9 article