%0 Conference Paper %B 2006 21st IEEE International Symposium On Defect and Fault Tolerance in VLSI Systems %D 2006 %T NoC interconnect yield improvement using crosspoint redundancy %A Grecu, C %A Ivanov, A %A Saleh, R %A Pande, P P %C Arlington, VA, USA %I IEEE Computer Society %K integrated circuit interconnections,integrated circuit reliability,integrated circuit yield,network-on-chip,redundancy %P 9 pp. %X Systems-on-chip integrate increasingly larger numbers of pre-designed cores interconnected through complex communication fabrics. For nanometer-scale VLSI processes (45 nm and below), it is difficult to guarantee correct fabrication with an acceptable yield without employing design techniques that take into account the intrinsic existence of manufacturing defects. In order to improve the yield and reliability of multi-core SoCs, their interconnect infrastructures must be designed such that fabrication and life-time faults can be tolerated. In this work we present a self-repair method for the interconnect fabrics of integrated multi-core systems. Our method is based on the use of redundant links and crosspoints, and improves both post-manufacturing yield and life-time reliability of on-chip communication fabrics. Our method can provide a significant interconnect yield improvement (up to 72\% in our experiments), and allows fine-tuning of yield versus redundant components %9 inproceedings