%0 Conference Paper %B Digest of Papers. Eleventh Annual 1993 IEEE VLSI Test Symposium (Cat. No.93TH0537-1) %D 1993 %T Minimal hardware multiple signature analysis for BIST %A Wu, Yuejian %A Ivanov, A %C Atlantic City, NJ, USA %I IEEE Comput. Soc. Press %K built-in self test,integrated logic circuits,logic testing %P 17-20 %U http://dx.doi.org/10.1109/VTEST.1993.313314 %X Proposes a new BIST multiple intermediate signature analysis scheme which checks n signatures against a single reference. Therefore, the circuitry for checking n signatures is essentially the same as that for checking one signature. The scheme is based on a manipulation of the CUT's fault-free output sequence. No circuit modification is required. The cost for implementing the scheme is a small nonrecurring CPU time expenditure in the design phase. In return, the scheme yields significant recurring silicon area savings, and reduced aliasing %9 inproceedings