%0 Journal Article %J IEEE Des. Test Comput. (USA) %D 2004 %T Jitter models for the design and test of Gbps-speed serial interconnects %A Ou, N %A Farahmand, T %A Kuo, A %A Tabatabaei, S %A Ivanov, A %K error statistics,jitter,logic design,logic testing %P 302-13 %U http://dx.doi.org/10.1109/MDT.2004.34 %V 21 %X We present a comprehensive analysis of jitter causes and types, and develops accurate jitter models for design and test of high-speed interconnects. The recent deployment of gigabit-per-second (Gbps) serial I/O interconnects aims at overcoming data transfer bottlenecks resulting from the limited ability to increase chip pin counts in parallel bus architectures. The traditional measure of a communication link's performance has been its associated bit error rate (BER), which is the ratio of the number of bits received in error to the total number of bits transmitted. When data rates increase, jitter magnitude and signal amplitude noise must decrease to maintain the same BER. As data rates exceed 1 Gbps, a slight increase in jitter or amplitude noise has a far greater effect on the BER %8 jul %9 article