%0 Journal Article %J Integr. VLSI J. (Netherlands) %D 2007 %T Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip %A Saleh, R %A Ebadi, Z S %A Avanaki, A N %A Ivanov, A %K design for testability,IEEE standards,integrated circuit testing,packet switching,system-on-chip %P 149-60 %U http://dx.doi.org/10.1016/j.vlsi.2006.02.002 %V 40 %X One of the difficult problems facing core-based system-on-chip (SoC) designs is test access. For testing the cores in an SoC, a special mechanism is required since they are not directly accessible via chip inputs and outputs. In this paper, we introduce a novel test access mechanism (TAM) based on time-division multiplexing (TDM). This so-called TDM-TAM is P1500 compatible and, in fact, uses a P1500 wrapper. The TAM advantages are its flexibility, scalability, and reconfigurability. Also this TAM could be very useful for testing multi-frequency cores in SoCs because, with TDM, the test data rate can be changed. The proposed TAM is compared with two other approaches: a serial threading approach analogous to the IEEE1149.1 standard (Serial TAM) and a packet-switching test network (called NIMA). A network processing unit is used as an SoC platform to compare the different TAMs. Results show that, in most cases, TDM is the most effective TAM in both test time and overhead area. [All rights reserved Elsevier] %8 feb %9 article