%0 Conference Paper %B 1993 Canadian Conference on Electrical and Computer Engineering (Cat. No.93TH0590-0) %D 1993 %T An integrated functional tester for CMOS logic %A Low, W %A Ivanov, A %C Vancouver, BC, Canada %I IEEE %K CMOS integrated circuits,encoding,functional analysis,integrated circuit testing,logic testing %P 453-6 %U http://dx.doi.org/10.1109/CCECE.1993.332196 %V vol.1 %X This paper presents the architecture of a functional tester system based on a functional tester chip (FTC) featuring per-pin programmability, output waveform formatting (NR, RC, RH, and RL), input window comparison and on-the-fly format switching. Waveforms are encoded using a set of simple 8-bit instructions. The bandwidth requirements of each channel is 8 bits per test vector. A four-channel FTC implemented using digital standard cells, with a 1.2 micron dual metal layer CMOS process, has a die size of 7?6 mm2 (core: 6?5 mm2). Each channel occupies approximately 17\% of the core area. Almost half the channel area is used by the format memory which provides a cache of the required timing and formats for a given test. Preliminary results based on measurements from an early version of the wave formatting circuit suggest that edge resolutions of at least 1.5 ns are possible %9 inproceedings