%0 Conference Paper %B 2005 Canadian Conference on Electrical and Computer Engineering %D 2006 %T An encoder for a 5GS/s 4-bit flash ADC in 0.18?m CMOS %A Sheikhaei, S %A Mirabbasi, S %A Ivanov, A %C Saskatoon, Sask., Canada %I IEEE %K analogue-digital conversion,CMOS logic circuits,current-mode logic,encoding %P 698-701 %X In this paper, a high-speed encoder intended for a 5GS/S 4-bit flash analog-to-digital converter (ADC) is presented. To meet the speed and power targets of the ADC, low-swing signaling is used in all the internal sub-blocks of the ADC including the encoder. To further enhance the speed performance of the encoder, 2-stage pipelining is utilized. In addition, the encoder is implemented in current mode logic (CML). The circuit is designed and simulated in a 0.18 ?m CMOS technology. It consumes 4 mW from a 1.8 V supply while operating at 5 GHz %9 inproceedings