%0 Conference Paper %B Proceedings 21st IEEE VLSI Test Symposium %D 2003 %T An embedded autonomous scan-based results analyzer (EARA) for SoC cores %A Nahvi, M %A Ivanov, A %C Napa, CA, USA %I IEEE Comput. Soc %K automatic test equipment,boundary scan testing,circuit simulation,integrated circuit design,integrated circuit testing,logic design,logic simulation,logic testing,system-on-chip %P 293-8 %U http://dx.doi.org/10.1109/VTEST.2003.1197666 %X Relying solely upon external ATE resources for scan test in complex SoC designs is increasingly difficult. In this work, we develop the concept and implementation of an embedded autonomous results analyzer (EARA) to be used in our modified dedicated autonomous scan-based testing (DAST) methodology. DAST introduces hierarchy and separates the functionality of ATE resources into two distinctive classes: a) test data communication; and b) test data control and observation. Consequently, test data control/observation functions are transferred to embedded blocks. In this work, we extend DAST to include the sending of expected test results along with the test stimulus to enable on-chip comparison. We present implementation results of EARA when applied to a number of SoC benchmarks %9 inproceedings