%0 Conference Paper %B Proceedings IEEE European Test Workshop. ETW 2001 %D 2001 %T A packet switching communication-based test access mechanism for system chips %A Nahvi, M %A Ivanov, A %C Stockholm, Sweden %I IEEE Comput. Soc %K application specific integrated circuits,automatic test pattern generation,built-in self test,embedded systems,integrated circuit testing,microprocessor chips,packet switching %P 81-6 %X In this paper, a Test Access Mechanism (TAM) architecture based on a packet switching communication network is presented. The basic goal is to develop a modular, generic, and configurable TAM. The proposed architecture provides a modular TAM that provides two levels of scalability, i.e., design-version scalability and multi-level scalability. Core access time and interconnect length models and simulation results for the proposed architecture are presented and compared to that of a bus-based TAM %9 inproceedings