@article { 2992314, title = {A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic}, journal = {IEEE J. Solid-State Circuits (USA)}, volume = {SC-22}, number = {4}, year = {1987}, note = {CMOS circuit techniques;differential cascode voltage switch logic;DCVS;conventional NAND/NOR logic;layout density;power dissipation;simulation;SPICE;input gate capacitance;propagation delay time;}, pages = {528 - 32}, type = {article}, abstract = {Differential cascode voltage switch (DCVS) logic is a CMOS circuit technique that has potential advantages over conventional NAND/NOR logic in terms of circuit delay, layout density, power dissipation, and logic flexibility. A detailed comparison of DCVS logic and conventional logic is carried out by simulation, using SPICE, of the performance of full adders designed using the different circuit techniques. The parameters compared are: input gate capacitance, number of transistors required, propagation delay time, and average power dissipation. In the static case, DCVS appears to be superior to full CMOS in regards to input capacitance and device count but inferior in regards to power dissipation. The speeds of the two technologies are similar. In the dynamic case, DCVS can be faster than more conventional CMOS dynamic logic, but only at the expense of increased device count and power dissipation}, keywords = {circuit analysis computing;CMOS integrated circuits;integrated logic circuits;}, author = { Chu, K.M. and Pulfrey, D.L.} }