@inproceedings { baosheng_wang_yi, title = {Yield, overall test environment timing accuracy, and defect level trade-offs for high-speed interconnect device testing}, journal = {Proceedings of the Twelfth Asian Symposium, ATS 2003}, year = {2003}, pages = {348-53}, publisher = {IEEE Comput. Soc}, organization = {IEEE Comput. Soc}, type = {inproceedings}, address = {Xi'an, China}, abstract = {This paper extends the model in (Wajih Dalai et al, Proc. of Int. Test Conf., p.518-523, 1999) to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixture impact. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80\% with a defect level of 300 DPM (defects per million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter}, keywords = {electronic equipment testing,interconnections,test equipment,timing}, URL = {http://dx.doi.org/10.1109/ATS.2003.1250835}, author = { Wang, Baosheng and Cho, Y.B. and Tabatabaei, S. and Ivanov, A.} }