@inproceedings { grecu_towards_20, title = {Towards open network-on-chip benchmarks}, journal = {2007 International Symposium on Networks-on-Chip}, year = {2007}, pages = {8 pp.}, publisher = {IEEE Computer Society}, organization = {IEEE Computer Society}, type = {inproceedings}, address = {Princeton, NJ, USA}, abstract = {Measuring and comparing performance, cost, and other features of advanced communication architectures for complex multi core/multiprocessor systems on chip is a significant challenge which has hardly been addressed so far. This document outlines the top-level view on a system of benchmarks for networks on chip (NoC), which intends to cover a wide spectrum of NoC design aspects, from application modeling to performance evaluation and post-manufacturing test and reliability. For performance benchmarking, requirements and features are described for application programs, synthetic micro-benchmarks, and abstract benchmark applications. Then, it proposes ways to measure and benchmark reliability, fault tolerance and testability of the on-chip communication fabric. This paper introduces the main concepts and ideas for benchmarking NoCs in a systematic and comparable way. It will be followed up by a report that will define a benchmark framework and the syntax of interfaces for benchmark programs that will allow the community to build-up a benchmark suite}, keywords = {benchmark testing,integrated circuit design,integrated circuit reliability,integrated circuit testing,network-on-chip}, author = { Grecu, C. and Ivanov, A. and Pande, R. and Jantsch, A. and Salminen, E. and Ogras, U. and Marculescu, R.} }