@inproceedings { wang_designs_200, title = {Designs for reducing test time of distributed small embedded SRAMs}, journal = {Proceedings. 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems}, year = {2004}, pages = {120-8}, publisher = {IEEE Comput. Soc}, organization = {IEEE Comput. Soc}, type = {inproceedings}, address = {Cannes, France}, abstract = {This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (e-SRAMs). This architecture improves the one proposed in (W. B. Jone et al, Proc. 17th IEEE VLSI Test Symp., p.246- 251, 1999 and also IEEE Transact. VLSI Syst., vol.10, no.4, p.512-515, 2002). The improvements are mainly two-fold. On one hand, the testing of time-consuming data retention faults (DRFs), that is neglected by the previously proposed test architecture, is now considered and performed via a DFT technique referred to as the "no write recovery test mode (XWRTM)". On the other hand, a parallel local response analyzer (LRA), instead of a serial response analyzer, is used to reduce the test time of these distributed small e-SRAMs. Results from our evaluations show that the proposed test architecture can achieve a better defect coverage and test time compared to those obtained previously, with a negligible area cost}, keywords = {design for testability,integrated circuit testing,logic testing,SRAM chips}, author = { Wang, B. and Wu, Y. and Ivanov, A.} }