@inproceedings { sheikhaei_encode, title = {An encoder for a 5GS/s 4-bit flash ADC in 0.18?m CMOS}, journal = {2005 Canadian Conference on Electrical and Computer Engineering}, year = {2006}, pages = {698-701}, publisher = {IEEE}, organization = {IEEE}, type = {inproceedings}, address = {Saskatoon, Sask., Canada}, abstract = {In this paper, a high-speed encoder intended for a 5GS/S 4-bit flash analog-to-digital converter (ADC) is presented. To meet the speed and power targets of the ADC, low-swing signaling is used in all the internal sub-blocks of the ADC including the encoder. To further enhance the speed performance of the encoder, 2-stage pipelining is utilized. In addition, the encoder is implemented in current mode logic (CML). The circuit is designed and simulated in a 0.18 ?m CMOS technology. It consumes 4 mW from a 1.8 V supply while operating at 5 GHz}, keywords = {analogue-digital conversion,CMOS logic circuits,current-mode logic,encoding}, author = { Sheikhaei, S. and Mirabbasi, S. and Ivanov, A.} }