@inproceedings { nahvi_packet_200, title = {A packet switching communication-based test access mechanism for system chips}, journal = {Proceedings IEEE European Test Workshop. ETW 2001}, year = {2001}, pages = {81-6}, publisher = {IEEE Comput. Soc}, organization = {IEEE Comput. Soc}, type = {inproceedings}, address = {Stockholm, Sweden}, abstract = {In this paper, a Test Access Mechanism (TAM) architecture based on a packet switching communication network is presented. The basic goal is to develop a modular, generic, and configurable TAM. The proposed architecture provides a modular TAM that provides two levels of scalability, i.e., design-version scalability and multi-level scalability. Core access time and interconnect length models and simulation results for the proposed architecture are presented and compared to that of a bus-based TAM}, keywords = {application specific integrated circuits,automatic test pattern generation,built-in self test,embedded systems,integrated circuit testing,microprocessor chips,packet switching}, author = { Nahvi, M. and Ivanov, A.} }