@inproceedings { sheikhaei_4-bit_, title = {A 4-bit 5 GS/s flash A/D converter in 0.18 ?m CMOS}, journal = {IEEE International Symposium on Circuits and Systems (ISCAS) (IEEE Cat. No. 05CH37618)}, volume = {Vol. 6}, year = {2005}, pages = {6138-41}, publisher = {IEEE}, organization = {IEEE}, type = {inproceedings}, address = {Kobe, Japan}, abstract = {A 4-bit 5 GS/s flash analog-to-digital converter (ADC) is designed and simulated in a 0.18 ?m CMOS technology. Low-swing operation both in the analog and the digital circuitry results in high-speed low power operation. The ADC dissipates 70 mW power from a 1.8 V supply while operating at 5 GHz. Offset averaging is used to minimize the effect of comparator offsets. Simulation results show that offset voltages with 67 mV standard deviation (i.e., 1 LSB) can be tolerated. Static INL and DNL errors are 0.34 LSB and 0.24 LSB respectively, and the ENOB is 3.65 bits. The simulation results of this non-time-interleaved flash ADC demonstrates a significant improvement in terms of power and area compared to those of previously reported ADCs}, keywords = {analogue-digital conversion,CMOS integrated circuits,comparators (circuits),low-power electronics}, author = { Sheikhaei, S. and Mirabbasi, S. and Ivanov, A.} }